Description: Successor to Power4 built in 0.13 um technology. The MCM (Multi Chip Module) includes 4 chips with two MultiThreaded cores each presenting a total of 16 virtual cores on the MCM. Each chip also has a 36 MB L3 cache attached for a total of 144 MB of L3 cache on the MCM. Each MCM can be connected to other MCMs through a 4GB/s bus for up to 128-way multiprocessing.
A single core version, also with Simultaneous MultiThreading, may also be launched. Each core includes 120 registers (80 on the Power4) and is said to have 40% to 100% better performance. Will later move to 90 nm with the Power5+ version.
Will be available 2004-06-11.
Die size 4 x 389 mm2 + L3 cache Bus speed GX+I/O >6GB/s L2 cache 4 x 3 x 640 KB L1 cache 4 x 64KB I; 32KB D Process 130 nm CuSOI Core speed 1.4 - 2 GHz Transistors 4 x 276 M + L3 cache Form factor 5400 pin L3 cache 4 x 36 MB (off-die, on MCM) Memory DDR / DDR-2 Type Server, 4 x 2 cores Core Power5
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