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IBM Power5

Introduced: 2004-06-11

Description: Successor to Power4 built in 0.13 um technology. The MCM (Multi Chip Module) includes 4 chips with two MultiThreaded cores each presenting a total of 16 virtual cores on the MCM. Each chip also has a 36 MB L3 cache attached for a total of 144 MB of L3 cache on the MCM. Each MCM can be connected to other MCMs through a 4GB/s bus for up to 128-way multiprocessing.

A single core version, also with Simultaneous MultiThreading, may also be launched. Each core includes 120 registers (80 on the Power4) and is said to have 40% to 100% better performance. Will later move to 90 nm with the Power5+ version.
Will be available 2004-06-11.

Type: Processors [Roadmap] [Timeline]

State: Released

Quick Specs

Die size4 x 389 mm2 + L3 cache
Bus speedGX+I/O >6GB/s
L2 cache4 x 3 x 640 KB
L1 cache4 x 64KB I; 32KB D
Process130 nm CuSOI
Core speed1.4 - 2 GHz
Transistors4 x 276 M + L3 cache
Form factor5400 pin
L3 cache4 x 36 MB (off-die, on MCM)
MemoryDDR / DDR-2
TypeServer, 4 x 2 cores

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News clips relating to IBM Power5

Showing 26-38 from 38 results. Page: [1 2 ]

2003-08-08 IBM's Power5+ to hit 3GHz The Register [rm]

2003-06-27 IBM claims it's running Power 5 servers already The Inquirer [rm]

2003-05-13 64-bit battle lines form The Inquirer [rm]

2003-04-11 IBM's Power 5 gets HP's full-FUD treatment The Inquirer [rm]

2003-04-01 IBM Power 5 very much alive: Power 6 on way The Inquirer [rm]

2003-02-26 Sun Details UltraSPARC Roadmap Ace's Hardware [rm]

2003-02-25 IBM Power5 will be multicore and multithread The Inquirer [rm]

2003-02-22 IBM weaves multithreading into Power5 Silicon Strategies [rm]

2003-02-19 Power5 boasts quadruple performance gain The Register [rm]

2003-02-17 Power5 to quadruple server brawn C/Net [rm]

2002-11-19 New Supercomputers Will Improve Nuke Test Simulations: 12544 IBM Power5 chips gives 360 TFlops InformationWeek [rm]

2002-04-29 IBM expands use of server chip C/Net [rm]

2002-04-25 IBM plots new Unix server chips C/Net [rm]

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