|Item||Intel Tanglewood / Tukwila||Intel Whitefield||Intel Dimona||Intel Montvale||Intel Tulsa||Intel Montecito||Intel Dempsey||Intel Cedar Mill||Intel Millington||Intel Sossaman|
|Die size||~580 mm2|
|Bus speed||667 / 800 MHz||533 / 667 MHz||1333 MHz||800 - 1066 MHz||533 / 667 MHz|
|L2 cache||4 x 6MB||2 * 1MB||2 x 2 MB||512 KB - 2 MB||2 MB (shared)|
|L1 cache||32 KB D; 32 KB I|
|Process||90 nm||65 nm||65 nm||65 nm|
|Core speed||1.6 GHz||3.80 GHz||>= 4.0 GHz||2.0 GHz (LV)|
|Power||100 W||~90 W||31W|
|Form factor||LGA775||478 μFC-PGA|
|Price||$696 - $3692||$423|
|L3 cache||8-16 MB||6 - 2 * 12 MB|
|Type||4-core||Server, Dual core||Server, 2 x EPIC,||Server, 2 cores||Desktop||Server, Dual Core|
2008 Intel Tanglewood / Tukwila
IA-64 processor originally said to have eight (plus one spare) cores per die and 16-32MB of cache to follow after Montecito. Appears to use parts from a follow-on project to the now canceled Alpha EV8. Said to arrive in 2006 or 2007 and offer "at least seven times the processing" power of Madison. Other rumours claim that HP wants their advanced math libraries on the die in silicon and that it might include a vector engine.
The 8+1 core version (designed in Hudson) is now said to be replaced by a 2-core version designed in Fort Collins.
Recently said to be renamed from Tanglewood to Tukwila due to copyright reasons.
Should use the new CSI bus and socket like Whitefield). Latest info indicates it will include 4 cores with 6x4 MB of L2 cache and an on-bord FB-DIMM memory controller..
2007-H2 Intel Whitefield
Low power, multi-core (4 x Banias with shared cache) server chip, possibly in the Xeon-line, succeeding Potomac, and Tulsa. 4 core version of / follow-on to Woodcrest. Said to be designed in India on a 65nm process, using the original Tanglewood interface. Includes CSI (Common System Interface) with embedded memory controllers to replace the DIB and compete with HyperTransport.
Said to be canceled. CSI will show up first in Tukwila.
Tom's claim that it is still alive.
2006-07-18 Intel Montecito
Dual core IA-64 processor with Switch on Event MultiThreading (SoEMT), (like Niagara) built on a 90 nm process. Expected to improve on Madison 9M's performance by 2.5 times. To include 2 * 1MB of L2 cache, 2 * 12MB of L3 cache and around 1.7 billion transistors.
Consumes "only" 100W. (Foxton was to clock it up to 2.0 GHz when it was running cool enough, but was canceled.)
The 2.0 GHz / 24 MB versions are delayed until Q2 2006.
Will be named 9000 (9015, 9020, 9030, 9040 and 9050). The 9010 is a single core version.
2006-Q2 Intel Dempsey Dual core server processor to succeed Irwindale. An MV Dempsey with a power demand of less than 105 W will also be out. Part of the Bensley platform. Some samples will be out this year. Uses the Greencreek and Blackford chipsets
2006-Q1 Intel Cedar Mill 65 nm processor Prescott-shrink, fill the gap between Prescott and Conroe. Said to be prepared for dual cores but will start off as a HyperThreading (dual threads) supporting single core chip. Newer info says that it is half a Presler. A value version with 512 KB of L2 cache, no HyperThreading and a slower bus is also rumoured.