Item IBM Power6 Sun UltraSparc V Fujitsu SPARC64 VI Power5+ Sun Gemini IBM Power5 Sun UltraSparc IV PowerPC 970
Release2007 2006 2006-H2 2005-10-04 2004 2004-06-11 2004-02-10 2003-06-23
Die size 19.1 x 20.3 mm 206 mm2 4 x 389 mm2 + L3 cache 356 mm2 121 (267) mm2
Bus speed GX+I/O >6GB/s Fireplane 150 MHz 1000 MHz, 6.4 GB/s
L2 cache 6-12 MB 6 MB 2 x 512 KB 4 x 3 x 640 KB 16 MB off die 512 KB 8-way SA
L1 cache D:64 KB 128 KB I, 128 KB D 4 x 64KB I; 32KB D D:64 KB, I:32 KB I:64 KB, D:32 KB 2-way SA
Process 65 nm SOI 90 nm 90 nm, Cu, 10 layer 90 nm 130 nm 130 nm CuSOI 130 nm 130 nm SOI
Core speed 4 - 4.5 GHz 1.8 - 3.0 GHz >2.4 GHz 1.9 GHz 1.2 GHz 1.4 - 2 GHz 1.2 GHz 1.8 GHz
Transistors 750 M 690 M 80 M 4 x 276 M + L3 cache 66 M 58 M+
Power 32 W 108 W 42 W @ 1.8 GHz
Form factor 360 pin 5400 pin LGA1368 576-CBGA
Core voltage 0.9 - 1.2V 1.0 / 1.8 V 1.35 V 1.3 V
Price
L3 cache 4 x 36 MB (off-die, on MCM)
Memory 128 bit 133 MHz DDR DDR / DDR-2 16 GB, 2.4 GB/s
Type Server Server Server, 2 cores Server, 4 x 2 cores Server, 2 cores Server
Core Olympus Gemini Power5 Jaguar Power4
Pipeline 2-stage 14-stage 23 stage
Platform
 

2007 IBM Power6 Successor to Power5+, due out in 2006 or 2007, boasting "very large frequency enhancements"... Expected to use a 65 nm process.

2006 Sun UltraSparc V Runs at more than 1.8 to above 3 GHz and is built using a 90 nm process. Five times faster than UltraSPARC III. Previously planned for 2005.

2006-H2 Fujitsu SPARC64 VI Dual core version of SPARC64 V built in a 90 nm process. Said to show in late 2005 or early 2006.

2005-10-04 Power5+ Quad-core, and multi-threaded successor to Power5 built in a 90 nm process and running at up to 1.9 GHz.

2004 Sun Gemini Sun Blade processor based on two UltraSparc II chips built on a 130 nm process

2004-06-11 IBM Power5 Successor to Power4 built in 0.13 um technology. The MCM (Multi Chip Module) includes 4 chips with two MultiThreaded cores each presenting a total of 16 virtual cores on the MCM. Each chip also has a 36 MB L3 cache attached for a total of 144 MB of L3 cache on the MCM. Each MCM can be connected to other MCMs through a 4GB/s bus for up to 128-way multiprocessing.

A single core version, also with Simultaneous MultiThreading, may also be launched. Each core includes 120 registers (80 on the Power4) and is said to have 40% to 100% better performance. Will later move to 90 nm with the Power5+ version.
Will be available 2004-06-11.

2004-02-10 Sun UltraSparc IV 4-way superscalar processor built with a 130 nm process running at 1.2 to 2 GHz. Consists of 2 UltraSPARC III pipelines. Pin compatible with UltraSPARC III. Previously code named Jaguar and planned for 03-H2. Later made in a 90 nm version.

2003-06-23 PowerPC 970 Single core version of the Power4 architecture also known as Power4+. Debuts at 1.4 - 1.8 GHz with a 900 MHz bus and more than 58 million transistors. It is built in a 0.13 um SoI / copper process. Bus bandwith 6.4 GB/s.