2004-11-08 Intel Fanwood / Madison 9M Upgraded Madison with 9 MB of L3 cache. Said to run at 1.6 GHz, and DP chips will include a bus speed increase to 533 MHz (earlier thought to be 667 or 800 MHz), while MP chips stay at 400 for now. The DP chip is called Fanwood while the MP chip is known as Madison 9M. Uses the E8870 chipset.
An upgraded Deerfield (a low voltage Itanium) will also be launched known as Fanwood LV. The first versions use the 400 MHz bus, while chips using a 667 MHz bus will show up in 2005-Q1.
2005-02-14 Intel Irwindale Prescott based DP processor with 2MB of L2 cache.
2005-04-18 Intel Pentium D Dual core processor replacing Tejas. Smithfield is the Workstation / gaming implementation of Paxville, part of the Lyndon platform. Uses the LGA775 socket and the Glenwood and Lakeport chipsets. Based on the NetBurst / Pentium 4 architecture but without HyperThreading. Basically two Pentium 4 chips on one die.
Launched in Q2 at 2.8, 3.0 and 3.2 GHz named 820 ($241), 830 ($316) and 840 ($530) respectively.
Launched as 'Pentium D' and 'Pentium EE', where EE adds HyperThreading.
2006-01-05 Intel Presler 65 nm chip dual core chip including Vanderpool (a virtualization technology) to succeed Smithfield. Likely to run at 3.6 GHz and above. Previously known as Blue Pressler. Is in fact two Cedar Mill chips bonded together. Uses the i975X chipset.
2006-01-05 Intel Yonah Mobile chip, succeeding Dothan in the power optimized notebook segment including HyperThreading and Vanderpool. Will use the Alviso-GM chipset. Includes one (Yonah1 - Core Solo) or two (Yonah2 - Core Duo) Dothan cores with one shared 2MB cache. The cache is dynamically divided between the cores. Runs on a 667 MHz bus, except for the ULV version which uses 533 MHz. Earlier listed as a 90nm chip in 04-H2.
Yonah (sometimes referred to as Jonah) is part of the Napa Centrino platform, succeeding Sonoma.
Named X50: $637, X40: $423, X30: $294, and X20: $241, while X48 and X39 will be low voltage versions.
There will also be a low-end Yonah called 756, below X20, with only one core running at 1.67 GHz and 2MB of cache.
Yonah will be used in future Macs.
Newer info names the chips T2600, T2500, T2400 and T2300 for normal chips, L2400 and L2300 for Low Voltage and U1400 and U1300 for Ultra Low Voltage. Clocked from 1.06 to 2.16 GHz.
2006-Q1 Intel Cedar Mill 65 nm processor Prescott-shrink, fill the gap between Prescott and Conroe. Said to be prepared for dual cores but will start off as a HyperThreading (dual threads) supporting single core chip. Newer info says that it is half a Presler. A value version with 512 KB of L2 cache, no HyperThreading and a slower bus is also rumoured.
2006-Q2 Intel Dempsey Dual core server processor to succeed Irwindale. An MV Dempsey with a power demand of less than 105 W will also be out. Part of the Bensley platform. Some samples will be out this year. Uses the Greencreek and Blackford chipsets
2006-07-18 Intel Montecito Dual core IA-64 processor with Switch on Event MultiThreading (SoEMT), (like Niagara) built on a 90 nm process. Expected to improve on Madison 9M's performance by 2.5 times. To include 2 * 1MB of L2 cache, 2 * 12MB of L3 cache and around 1.7 billion transistors.
Consumes "only" 100W. (Foxton was to clock it up to 2.0 GHz when it was running cool enough, but was canceled.)
The 2.0 GHz / 24 MB versions are delayed until Q2 2006.
Will be named 9000 (9015, 9020, 9030, 9040 and 9050). The 9010 is a single core version.
2007-H2 Intel Whitefield Low power, multi-core (4 x Banias with shared cache) server chip, possibly in the Xeon-line, succeeding Potomac, and Tulsa. 4 core version of / follow-on to Woodcrest. Said to be designed in India on a 65nm process, using the original Tanglewood interface. Includes CSI (Common System Interface) with embedded memory controllers to replace the DIB and compete with HyperTransport.
Said to be canceled. CSI will show up first in Tukwila.
Tom's claim that it is still alive.
2008 Intel Tanglewood / Tukwila IA-64 processor originally said to have eight (plus one spare) cores per die and 16-32MB of cache to follow after Montecito. Appears to use parts from a follow-on project to the now canceled Alpha EV8. Said to arrive in 2006 or 2007 and offer "at least seven times the processing" power of Madison. Other rumours claim that HP wants their advanced math libraries on the die in silicon and that it might include a vector engine.
The 8+1 core version (designed in Hudson) is now said to be replaced by a 2-core version designed in Fort Collins.
Recently said to be renamed from Tanglewood to Tukwila due to copyright reasons.
Should use the new CSI bus and socket like Whitefield). Latest info indicates it will include 4 cores with 6x4 MB of L2 cache and an on-bord FB-DIMM memory controller..