2006-01-05 Intel Yonah Mobile chip, succeeding Dothan in the power optimized notebook segment including HyperThreading and Vanderpool. Will use the Alviso-GM chipset. Includes one (Yonah1 - Core Solo) or two (Yonah2 - Core Duo) Dothan cores with one shared 2MB cache. The cache is dynamically divided between the cores. Runs on a 667 MHz bus, except for the ULV version which uses 533 MHz. Earlier listed as a 90nm chip in 04-H2.
Yonah (sometimes referred to as Jonah) is part of the Napa Centrino platform, succeeding Sonoma.
Named X50: $637, X40: $423, X30: $294, and X20: $241, while X48 and X39 will be low voltage versions.
There will also be a low-end Yonah called 756, below X20, with only one core running at 1.67 GHz and 2MB of cache.
Yonah will be used in future Macs.
Newer info names the chips T2600, T2500, T2400 and T2300 for normal chips, L2400 and L2300 for Low Voltage and U1400 and U1300 for Ultra Low Voltage. Clocked from 1.06 to 2.16 GHz.
2006-06-19 Intel Woodcrest DP server version of Conroe. Will have FBD (Fully Buffered DIMM) which is said to allow for "stupidly large amounts of RAM". Said to be planned for future Macs. Will be named 5160, 5150, 5140, 5130, 5120 and 5110.
2006-07-27 Intel Conroe Major redesign of the desktop chips based on the mobile chip Merom. Should use the same bus as Merom and Tukwila. Part of the Averill platform. Said to be used in future Macs. Will be named E6300 (1.86 GHz, 2MB, $210), E6400 (2.13 GHz, 2MB, $230), E6600 (2.40 GHz, 4MB, $315) and E6700 (2.67 GHz, 1066 MHz, 4MB, $529). A value-segment version known as Conroe-L will be introduced in 2007-Q2. Will also be used in Uniprocessor Xeon chips (3040, 3050, 3060, 3070)
2006-07-27 Intel Merom Mobile processor succeeding Prescott-M and Yonah built on a 65 nm process. Accompanied by the Crestine chipset. Recent rumours claim that Merom is a major new core design with multiple cores and, depending on version, 2-4 MB of cache, which will also form the base for the next desktop chip, Conroe. Said to consume about 45W.
Earlier said to launch in 05-H2 or 2007, prototype chips has been out since May of 2006.
Merom is part of the Santa Rosa Centrino platform, succeeding Napa. Said to be used in future Macs.
Bus speed to go up to 800 MHz in 2007-H1.
Will be named T7600, the T7400, the T7200 and T5600.
2007-H1 Intel Clovertown Server-version of Allendale. 4-core chip with 4MB of cache. (Previously referred to as Cloverton.) Claimed to be 2 Woodcrest cores in one package. Part of the Stoakley platform. Uses the Seaburg chipset.
2007-H2 Intel Whitefield Low power, multi-core (4 x Banias with shared cache) server chip, possibly in the Xeon-line, succeeding Potomac, and Tulsa. 4 core version of / follow-on to Woodcrest. Said to be designed in India on a 65nm process, using the original Tanglewood interface. Includes CSI (Common System Interface) with embedded memory controllers to replace the DIB and compete with HyperTransport.
Said to be canceled. CSI will show up first in Tukwila.
Tom's claim that it is still alive.
2008 Intel Hapertown Octa-core chip with 12 MB of shared L2 cache, built in the 45 nm process.
2008 Intel Yorkfield Chip with 8 cores on more than one die for the desktop. 12 MB shared L2 cache.
2008 Intel Ridgefield Dual core chip on one die for the desktop. Includes 6MB of L2 cache.
2008 Intel Wolfdale Dual cores on a single die with 3 MB of shared L2 cache.