2005-12-23 Intel's multi-FSB chipsets go back to the future

Link to story (The Inquirer)

Other news this month

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2003-01-14 Alpha 21364 EV7 Also known as Marvel, the EV7 extends the EV6 core with on-chip L2 cache. Supports "glueless" SMP, RAMBUS, etc.

2006-Q1 Intel Blackford Xeon chipset succeeding Lindenhurst. Supports the Dual Independent Bus (DIB, 2S platform) and Dempsey.

2006-06-19 Intel Woodcrest DP server version of Conroe. Will have FBD (Fully Buffered DIMM) which is said to allow for "stupidly large amounts of RAM". Said to be planned for future Macs. Will be named 5160, 5150, 5140, 5130, 5120 and 5110.

2006-Q2 Intel Dempsey Dual core server processor to succeed Irwindale. An MV Dempsey with a power demand of less than 105 W will also be out. Part of the Bensley platform. Some samples will be out this year. Uses the Greencreek and Blackford chipsets

2007 Intel Clarksboro Chipset in the Caneland platform matching the Tigerton, Dunnington processors. First chip to include an FBDIMM interface.

2007 Intel Tigerton New server processor in the Caneland platform. Possibly merged with Dunnington as it is sometimes referred to as Tigerton Dunnington.

2008 Intel Common System Interface New bus to compete with HyperTransport for both Pentium and Itanium chips. Processors said to add embedded memory controllers. Delayed from 2007 until perhaps 2009? Said to be included in Tukwila.

2008 Intel Tanglewood / Tukwila IA-64 processor originally said to have eight (plus one spare) cores per die and 16-32MB of cache to follow after Montecito. Appears to use parts from a follow-on project to the now canceled Alpha EV8. Said to arrive in 2006 or 2007 and offer "at least seven times the processing" power of Madison. Other rumours claim that HP wants their advanced math libraries on the die in silicon and that it might include a vector engine.
The 8+1 core version (designed in Hudson) is now said to be replaced by a 2-core version designed in Fort Collins.
Recently said to be renamed from Tanglewood to Tukwila due to copyright reasons.
Should use the new CSI bus and socket like Whitefield). Latest info indicates it will include 4 cores with 6x4 MB of L2 cache and an on-bord FB-DIMM memory controller..

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