2006-02-10 Intel promises quad server chips for Q1 2007

Link to story (The Inquirer)

Other news this month

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2003-06-30 Intel Madison Copper based 0.13 micron IA-64 follow-up to McKinley for 4- to 8-way servers. Sports 6MB of L3 cache. Said to deliver 30-50% better performace than McKinley. Will include around 410 million transistors on a 374 mm2 chip and consume 130W. The 6MB@1.5GHz version costs $4226, the 4MB@1.4GHz (Deerfield) $2247.

2006-06-19 Intel Woodcrest DP server version of Conroe. Will have FBD (Fully Buffered DIMM) which is said to allow for "stupidly large amounts of RAM". Said to be planned for future Macs. Will be named 5160, 5150, 5140, 5130, 5120 and 5110.

2006-Q2 Intel Dempsey Dual core server processor to succeed Irwindale. An MV Dempsey with a power demand of less than 105 W will also be out. Part of the Bensley platform. Some samples will be out this year. Uses the Greencreek and Blackford chipsets

2006-07-18 Intel Montecito Dual core IA-64 processor with Switch on Event MultiThreading (SoEMT), (like Niagara) built on a 90 nm process. Expected to improve on Madison 9M's performance by 2.5 times. To include 2 * 1MB of L2 cache, 2 * 12MB of L3 cache and around 1.7 billion transistors.
Consumes "only" 100W. (Foxton was to clock it up to 2.0 GHz when it was running cool enough, but was canceled.)
The 2.0 GHz / 24 MB versions are delayed until Q2 2006.
Will be named 9000 (9015, 9020, 9030, 9040 and 9050). The 9010 is a single core version.

2006-07-27 Intel Conroe Major redesign of the desktop chips based on the mobile chip Merom. Should use the same bus as Merom and Tukwila. Part of the Averill platform. Said to be used in future Macs. Will be named E6300 (1.86 GHz, 2MB, $210), E6400 (2.13 GHz, 2MB, $230), E6600 (2.40 GHz, 4MB, $315) and E6700 (2.67 GHz, 1066 MHz, 4MB, $529). A value-segment version known as Conroe-L will be introduced in 2007-Q2. Will also be used in Uniprocessor Xeon chips (3040, 3050, 3060, 3070)

2006-Q3 Intel Tulsa Dual-core IA-32 server chip in the Xeon class, succeeding Potomac to launch in 2006. Based on two Netburst cores with Hyperthreading.

2007-H1 Intel Clovertown Server-version of Allendale. 4-core chip with 4MB of cache. (Previously referred to as Cloverton.) Claimed to be 2 Woodcrest cores in one package. Part of the Stoakley platform. Uses the Seaburg chipset.

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