2006-06-19 Intel Woodcrest DP server version of Conroe. Will have FBD (Fully Buffered DIMM) which is said to allow for "stupidly large amounts of RAM". Said to be planned for future Macs. Will be named 5160, 5150, 5140, 5130, 5120 and 5110.
2006-07-18 Intel Montecito Dual core IA-64 processor with Switch on Event MultiThreading (SoEMT), (like Niagara) built on a 90 nm process. Expected to improve on Madison 9M's performance by 2.5 times. To include 2 * 1MB of L2 cache, 2 * 12MB of L3 cache and around 1.7 billion transistors.
Consumes "only" 100W. (Foxton was to clock it up to 2.0 GHz when it was running cool enough, but was canceled.)
The 2.0 GHz / 24 MB versions are delayed until Q2 2006.
Will be named 9000 (9015, 9020, 9030, 9040 and 9050). The 9010 is a single core version.
2007-H1 Intel Clovertown Server-version of Allendale. 4-core chip with 4MB of cache. (Previously referred to as Cloverton.) Claimed to be 2 Woodcrest cores in one package. Part of the Stoakley platform. Uses the Seaburg chipset.