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2001-05-29 Intel Itanium The first processor (formerly known as Merced) coming out of the HP / Intel cooperation. Introduces the IA-64 architecture, using the EPIC (Explicitly Parallel Instruction Computing) technology. IA-64 leaves the optimization work to the compiler but the compiled code includes information about inherent parallelism. This has the drawback of making compiled code more processor specific (optimization-wise), but reduces the need to fill the chip with logic to analyze and reorganize the code during runtime.
It remains to be seen how Intel has been able to balance the architecture. It will also be IA-32 compatible in hardware, although later IA-64 products may use software translation. Merced will include a three level cache, adding a level-0 cache. 2 to 4 MB of L2 cache will be included.
Expected to include around 3 - 4 floating point units (for 3 G flops at extended precision, and 6 G flops at single precision) allowing for 6 - 8 parallel instruction for performance three times Tanner while the die size may run up to 300 mm2 using a 0.18 um process.
Start at 733 and 800 MHz clock speed with a 128 bit bus in a MCM package most likely running at 200 (266?) MHz, providing a peak bandwidth of 3.2 Gb/s. Still uses PC100 memory. Priced between $1500 to >$4000.