2002-06-27 Intel's AMD X86-64 clone, doggone it

Link to story (The Inquirer)

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2004-02-02 Intel Pentium 4E Also known as Prescott launches at 2.8 ($178), 3.0 ($218), 3.2 ($278) and 3.4 ($417) GHz with a 800 MHz front side bus and is built using a seven layer, Low-K, 90 nm Strained Silicon process.
Builds on the Netburst architecture, but adds "PNI" or Prescott New Instructions, which includes 11 new instructions, and LaGrande, a new security interface to go with Microsoft's Palladium. Also includes an improved pre-fetch branch predictor, improved HyperThreading, doubled L1 data cache size, doubled RAT History table size and advanced power manangement.
Will use Canterwood to start with, but in Q2 it will add the 64-bit CT Technology, move to Grantsdale and use the LGA775 socket.
Celeron Prescotts will be launched in Q2. Prescott reach 4 GHz in 2004-Q4 (now moved to 2005-Q1).
Now renamed Pentium 4E.

2004-03-11 Intel Yamhill The Intel 64-bit technology is called Intel Extended Memory 64 Technology (EM64T), 'CT' or IA32e and was previewed at IDF 2004.
Project was said to have been called *T ("star-T"?). IA32e is said to be largely compatible with AMD64, which is probably connected to the rumour that Microsoft is quoted as saying that they "will not support more than one 64-bit extension to the x86 platform" or something similar.
Will be launched for Nocona and Prescott LGA775.

2005-Q2 Intel Tejas Successor to Prescott likely to be called Pentium V built on a 90 nm process, supporting IA-32e, DDR-II and PCI Express. Runs cooler and quiter than current chips. Uses a new LGA775 socket, with a 1066 MHz bus and starts at around 4.5 GHz, moving to around 9 before it is canceled. To include the 8 new "Tejas New Instructions" aka Azalia (Azalea), for improved audio multistreaming, speech recognition, Dolby Digital etc. Also includes "Extended Enhanced HyperThreading"...
Uses dual channel DDR-II DRAM at 533 MHz and the Alderwood and Grantsdale chipsets.
Will later be built in a 65 nm process, with a size of 80-100 mm2. The 65 nm version will get 2 MB of L2 cache on chip.
Earlier listed for a 04-Q4 launch, but recent news claim Prescott delays have moved the launch into 2005.
Tejas is canned in favor of Merom / Conroe.

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