2003-10-14 Transmeta Efficeon Next Generation Transmeta "New Crusoe" (aka Astro or TM8000) chip based on a new architecture issuing eight 32 bit instructions per clock, making it a 256 bit VLIW chip. Includes HyperTransport, AGP4x and DDR400 interfaces in a North Bridge directly on the chip. Includes 1 MB of L2 cache which gives a die size of just over 100 mm2 with the 130 nm process (68 mm2 @ 90 nm). Shown at MPF, but ship date is still unknown.
In H2 of 2004 a 90 nm version called TM8800 with 2 MB of cache consuming 3W at 1 GHz and 25W at 2 GHz will be launched.