2003-05-13 64-bit battle lines form

Link to story (The Inquirer)

Other news this month

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2003-04-22 AMD Opteron AMD's 64 bit extension to IA-32 aka Sledgehammer or Hammer. 0.13 micron chip using "HyperTransport" for internal data traffic, a NUMA (Non-Uniform Memory Access) bus to speed up large multiprocessor systems. The version with 1 MB of L2 cache includes 100 million transistors on an area of around 180 mm2.

Starts at 1.8 GHz and consumes about 70W of power. Later, 1.8 and 2 GHz chips will be released, followed by 2.2 GHz, 2.4 and 2.6 GHz. Server prices are rumoured to start at $3000 to $6000.

Three types available: 8xx, for up to eight-way servers, 2xx for dual servers and 1xx for single processor systems. The xx is a subjective performance number.

In April, Opteron 240 ($283), 242 ($690), and 244 ($794) was launched.
On 03-06-30 the 840, 842, 844 ($749-$2149), 140, 142 and 144 ($229-669) were released.
On 03-09-09 the 146 and 846 were released.

2003-06-23 PowerPC 970 Single core version of the Power4 architecture also known as Power4+. Debuts at 1.4 - 1.8 GHz with a 900 MHz bus and more than 58 million transistors. It is built in a 0.13 um SoI / copper process. Bus bandwith 6.4 GB/s.

2003-06-30 Intel Madison Copper based 0.13 micron IA-64 follow-up to McKinley for 4- to 8-way servers. Sports 6MB of L3 cache. Said to deliver 30-50% better performace than McKinley. Will include around 410 million transistors on a 374 mm2 chip and consume 130W. The 6MB@1.5GHz version costs $4226, the 4MB@1.4GHz (Deerfield) $2247.

2004-02-10 Sun UltraSparc IV 4-way superscalar processor built with a 130 nm process running at 1.2 to 2 GHz. Consists of 2 UltraSPARC III pipelines. Pin compatible with UltraSPARC III. Previously code named Jaguar and planned for 03-H2. Later made in a 90 nm version.

2004-Q1 Alpha EV79 The EV79 was originally meant to replace the earlier planned, much more ambitious, EV8 in early 2004. EV79 would have been the last update of the Alpha architecture but has now been killed off in favor of the less ambitious EV7z. Would have been made in a 130 nm SOI process with a die size of 300 mm2 and run at above 1.6 GHz .

2004-06-11 IBM Power5 Successor to Power4 built in 0.13 um technology. The MCM (Multi Chip Module) includes 4 chips with two MultiThreaded cores each presenting a total of 16 virtual cores on the MCM. Each chip also has a 36 MB L3 cache attached for a total of 144 MB of L3 cache on the MCM. Each MCM can be connected to other MCMs through a 4GB/s bus for up to 128-way multiprocessing.

A single core version, also with Simultaneous MultiThreading, may also be launched. Each core includes 120 registers (80 on the Power4) and is said to have 40% to 100% better performance. Will later move to 90 nm with the Power5+ version.
Will be available 2004-06-11.

2004-11-08 Intel Fanwood / Madison 9M Upgraded Madison with 9 MB of L3 cache. Said to run at 1.6 GHz, and DP chips will include a bus speed increase to 533 MHz (earlier thought to be 667 or 800 MHz), while MP chips stay at 400 for now. The DP chip is called Fanwood while the MP chip is known as Madison 9M. Uses the E8870 chipset.
An upgraded Deerfield (a low voltage Itanium) will also be launched known as Fanwood LV. The first versions use the 400 MHz bus, while chips using a 667 MHz bus will show up in 2005-Q1.

2005-10-04 Power5+ Quad-core, and multi-threaded successor to Power5 built in a 90 nm process and running at up to 1.9 GHz.

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