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2003-08-20 IBM: Power5 Chip to Tap Threading

Link to story (ExtremeTech)

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2004-06-11 IBM Power5 Successor to Power4 built in 0.13 um technology. The MCM (Multi Chip Module) includes 4 chips with two MultiThreaded cores each presenting a total of 16 virtual cores on the MCM. Each chip also has a 36 MB L3 cache attached for a total of 144 MB of L3 cache on the MCM. Each MCM can be connected to other MCMs through a 4GB/s bus for up to 128-way multiprocessing.

A single core version, also with Simultaneous MultiThreading, may also be launched. Each core includes 120 registers (80 on the Power4) and is said to have 40% to 100% better performance. Will later move to 90 nm with the Power5+ version.
Will be available 2004-06-11.