2006-07-18 Intel Montecito Dual core IA-64 processor with Switch on Event MultiThreading (SoEMT), (like Niagara) built on a 90 nm process. Expected to improve on Madison 9M's performance by 2.5 times. To include 2 * 1MB of L2 cache, 2 * 12MB of L3 cache and around 1.7 billion transistors.
Consumes "only" 100W. (Foxton was to clock it up to 2.0 GHz when it was running cool enough, but was canceled.)
The 2.0 GHz / 24 MB versions are delayed until Q2 2006.
Will be named 9000 (9015, 9020, 9030, 9040 and 9050). The 9010 is a single core version.
2008 Intel Nehalem Nehalem was a new design built using a 65 nm process with half the die size of a Northwood. Was supposed to use a 1200 MHz (or a 4 GHz bus as some rumours claim) bus and start at 9.60 GHz before continuing to 10 GHz+.
Nehalem is now changed to be the name of the family succeeding Merom, Conroe and Woodcrest, which is 45nm and will include Whitefield, Gainstown and Bloomfield. The Nehalem platform will use the Tylersburg chipset