2004-01-26 Intel's Prescott reveals its process problems

Link to story (The Inquirer)

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2004-02-02 Intel Pentium 4E Also known as Prescott launches at 2.8 ($178), 3.0 ($218), 3.2 ($278) and 3.4 ($417) GHz with a 800 MHz front side bus and is built using a seven layer, Low-K, 90 nm Strained Silicon process.
Builds on the Netburst architecture, but adds "PNI" or Prescott New Instructions, which includes 11 new instructions, and LaGrande, a new security interface to go with Microsoft's Palladium. Also includes an improved pre-fetch branch predictor, improved HyperThreading, doubled L1 data cache size, doubled RAT History table size and advanced power manangement.
Will use Canterwood to start with, but in Q2 it will add the 64-bit CT Technology, move to Grantsdale and use the LGA775 socket.
Celeron Prescotts will be launched in Q2. Prescott reach 4 GHz in 2004-Q4 (now moved to 2005-Q1).
Now renamed Pentium 4E.

2004-05-10 Intel Dothan 90 nm successor to Banias, and the Centrino / Pentium M line, which will have a 400 MHz bus (533 in 05-Q1) and 2MB of cache. Will be called 735, 745 and 755 for 1.7 to 2.0 GHz processors costing $294, $423 and $637.
Slower (715 and 725) versions launch in Q3, and faster (760, 770: 533 MHz bus, up to 2.13 GHz) in Q4. Consumes 21W in performance mode. Earlier meant to launch in 03-Q3.

2005-Q2 Intel Tejas Successor to Prescott likely to be called Pentium V built on a 90 nm process, supporting IA-32e, DDR-II and PCI Express. Runs cooler and quiter than current chips. Uses a new LGA775 socket, with a 1066 MHz bus and starts at around 4.5 GHz, moving to around 9 before it is canceled. To include the 8 new "Tejas New Instructions" aka Azalia (Azalea), for improved audio multistreaming, speech recognition, Dolby Digital etc. Also includes "Extended Enhanced HyperThreading"...
Uses dual channel DDR-II DRAM at 533 MHz and the Alderwood and Grantsdale chipsets.
Will later be built in a 65 nm process, with a size of 80-100 mm2. The 65 nm version will get 2 MB of L2 cache on chip.
Earlier listed for a 04-Q4 launch, but recent news claim Prescott delays have moved the launch into 2005.
Tejas is canned in favor of Merom / Conroe.

2006-01-05 Intel Yonah Mobile chip, succeeding Dothan in the power optimized notebook segment including HyperThreading and Vanderpool. Will use the Alviso-GM chipset. Includes one (Yonah1 - Core Solo) or two (Yonah2 - Core Duo) Dothan cores with one shared 2MB cache. The cache is dynamically divided between the cores. Runs on a 667 MHz bus, except for the ULV version which uses 533 MHz. Earlier listed as a 90nm chip in 04-H2.
Yonah (sometimes referred to as Jonah) is part of the Napa Centrino platform, succeeding Sonoma.
Named X50: $637, X40: $423, X30: $294, and X20: $241, while X48 and X39 will be low voltage versions.
There will also be a low-end Yonah called 756, below X20, with only one core running at 1.67 GHz and 2MB of cache.
Yonah will be used in future Macs.
Newer info names the chips T2600, T2500, T2400 and T2300 for normal chips, L2400 and L2300 for Low Voltage and U1400 and U1300 for Ultra Low Voltage. Clocked from 1.06 to 2.16 GHz.

2006-07-27 Intel Merom Mobile processor succeeding Prescott-M and Yonah built on a 65 nm process. Accompanied by the Crestine chipset. Recent rumours claim that Merom is a major new core design with multiple cores and, depending on version, 2-4 MB of cache, which will also form the base for the next desktop chip, Conroe. Said to consume about 45W.
Earlier said to launch in 05-H2 or 2007, prototype chips has been out since May of 2006.
Merom is part of the Santa Rosa Centrino platform, succeeding Napa. Said to be used in future Macs.
Bus speed to go up to 800 MHz in 2007-H1.
Will be named T7600, the T7400, the T7200 and T5600.

2006 Intel Gilo Mobile processor, succeeding Merom. Built in a 65 nm process.

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