2003-06-30 Intel Madison Copper based 0.13 micron IA-64 follow-up to McKinley for 4- to 8-way servers. Sports 6MB of L3 cache. Said to deliver 30-50% better performace than McKinley. Will include around 410 million transistors on a 374 mm2 chip and consume 130W. The 6MB@1.5GHz version costs $4226, the 4MB@1.4GHz (Deerfield) $2247.
2004-02-02 Intel Pentium 4E Also known as Prescott launches at 2.8 ($178), 3.0 ($218), 3.2 ($278) and 3.4 ($417) GHz with a 800 MHz front side bus and is built using a seven layer, Low-K, 90 nm Strained Silicon process.
Builds on the Netburst architecture, but adds "PNI" or Prescott New Instructions, which includes 11 new instructions, and LaGrande, a new security interface to go with Microsoft's Palladium. Also includes an improved pre-fetch branch predictor, improved HyperThreading, doubled L1 data cache size, doubled RAT History table size and advanced power manangement.
Will use Canterwood to start with, but in Q2 it will add the 64-bit CT Technology, move to Grantsdale and use the LGA775 socket.
Celeron Prescotts will be launched in Q2. Prescott reach 4 GHz in 2004-Q4 (now moved to 2005-Q1).
Now renamed Pentium 4E.
2004-06-28 Intel Nocona Xeon DP variety of Prescott made with the 90 nm process. Uses the Tumwater and Lindenhurst chipsets with a 800 MHz bus. Includes HyperThreading, SSE3 and the 64-bit EM64T (earlier CT, Yamhill, AMD64) Technology.
2004-11-08 Intel Fanwood / Madison 9M Upgraded Madison with 9 MB of L3 cache. Said to run at 1.6 GHz, and DP chips will include a bus speed increase to 533 MHz (earlier thought to be 667 or 800 MHz), while MP chips stay at 400 for now. The DP chip is called Fanwood while the MP chip is known as Madison 9M. Uses the E8870 chipset.
An upgraded Deerfield (a low voltage Itanium) will also be launched known as Fanwood LV. The first versions use the 400 MHz bus, while chips using a 667 MHz bus will show up in 2005-Q1.
2005-Q2 Intel Tejas Successor to Prescott likely to be called Pentium V built on a 90 nm process, supporting IA-32e, DDR-II and PCI Express. Runs cooler and quiter than current chips. Uses a new LGA775 socket, with a 1066 MHz bus and starts at around 4.5 GHz, moving to around 9 before it is canceled. To include the 8 new "Tejas New Instructions" aka Azalia (Azalea), for improved audio multistreaming, speech recognition, Dolby Digital etc. Also includes "Extended Enhanced HyperThreading"...
Uses dual channel DDR-II DRAM at 533 MHz and the Alderwood and Grantsdale chipsets.
Will later be built in a 65 nm process, with a size of 80-100 mm2. The 65 nm version will get 2 MB of L2 cache on chip.
Earlier listed for a 04-Q4 launch, but recent news claim Prescott delays have moved the launch into 2005.
Tejas is canned in favor of Merom / Conroe.