2004-06-28 Intel Nocona Xeon DP variety of Prescott made with the 90 nm process. Uses the Tumwater and Lindenhurst chipsets with a 800 MHz bus. Includes HyperThreading, SSE3 and the 64-bit EM64T (earlier CT, Yamhill, AMD64) Technology.
2004-11-08 Intel Fanwood / Madison 9M Upgraded Madison with 9 MB of L3 cache. Said to run at 1.6 GHz, and DP chips will include a bus speed increase to 533 MHz (earlier thought to be 667 or 800 MHz), while MP chips stay at 400 for now. The DP chip is called Fanwood while the MP chip is known as Madison 9M. Uses the E8870 chipset.
An upgraded Deerfield (a low voltage Itanium) will also be launched known as Fanwood LV. The first versions use the 400 MHz bus, while chips using a 667 MHz bus will show up in 2005-Q1.
2005-03-29 Intel Potomac Prescott based chip for 4- and 8-processor servers. Will have the EM64T bit extensions. Starts at 3.33 GHz and includes 8 MB of L3 cache. Uses the Twin Castle chipset. Part of the Truland platform
2005-Q2 Intel Tejas Successor to Prescott likely to be called Pentium V built on a 90 nm process, supporting IA-32e, DDR-II and PCI Express. Runs cooler and quiter than current chips. Uses a new LGA775 socket, with a 1066 MHz bus and starts at around 4.5 GHz, moving to around 9 before it is canceled. To include the 8 new "Tejas New Instructions" aka Azalia (Azalea), for improved audio multistreaming, speech recognition, Dolby Digital etc. Also includes "Extended Enhanced HyperThreading"...
Uses dual channel DDR-II DRAM at 533 MHz and the Alderwood and Grantsdale chipsets.
Will later be built in a 65 nm process, with a size of 80-100 mm2. The 65 nm version will get 2 MB of L2 cache on chip.
Earlier listed for a 04-Q4 launch, but recent news claim Prescott delays have moved the launch into 2005.
Tejas is canned in favor of Merom / Conroe.
2006-07-18 Intel Montecito Dual core IA-64 processor with Switch on Event MultiThreading (SoEMT), (like Niagara) built on a 90 nm process. Expected to improve on Madison 9M's performance by 2.5 times. To include 2 * 1MB of L2 cache, 2 * 12MB of L3 cache and around 1.7 billion transistors.
Consumes "only" 100W. (Foxton was to clock it up to 2.0 GHz when it was running cool enough, but was canceled.)
The 2.0 GHz / 24 MB versions are delayed until Q2 2006.
Will be named 9000 (9015, 9020, 9030, 9040 and 9050). The 9010 is a single core version.
2008 Intel Tanglewood / Tukwila IA-64 processor originally said to have eight (plus one spare) cores per die and 16-32MB of cache to follow after Montecito. Appears to use parts from a follow-on project to the now canceled Alpha EV8. Said to arrive in 2006 or 2007 and offer "at least seven times the processing" power of Madison. Other rumours claim that HP wants their advanced math libraries on the die in silicon and that it might include a vector engine.
The 8+1 core version (designed in Hudson) is now said to be replaced by a 2-core version designed in Fort Collins.
Recently said to be renamed from Tanglewood to Tukwila due to copyright reasons.
Should use the new CSI bus and socket like Whitefield). Latest info indicates it will include 4 cores with 6x4 MB of L2 cache and an on-bord FB-DIMM memory controller..
2008 Intel Nehalem Nehalem was a new design built using a 65 nm process with half the die size of a Northwood. Was supposed to use a 1200 MHz (or a 4 GHz bus as some rumours claim) bus and start at 9.60 GHz before continuing to 10 GHz+.
Nehalem is now changed to be the name of the family succeeding Merom, Conroe and Woodcrest, which is 45nm and will include Whitefield, Gainstown and Bloomfield. The Nehalem platform will use the Tylersburg chipset