2002-07-08 Intel E8870 Server chipset formerly known as 870 supporting up to 4 McKinley chips. In combination with the "Scalability Port Switch" it becomes E9870, supporting up to 16 processors. Other switches may be used for up to 512 processor configurations. South bridge: SIOH/ICH4.
2004-06-28 Intel Nocona Xeon DP variety of Prescott made with the 90 nm process. Uses the Tumwater and Lindenhurst chipsets with a 800 MHz bus. Includes HyperThreading, SSE3 and the 64-bit EM64T (earlier CT, Yamhill, AMD64) Technology.
2004-11-08 Intel Fanwood / Madison 9M Upgraded Madison with 9 MB of L3 cache. Said to run at 1.6 GHz, and DP chips will include a bus speed increase to 533 MHz (earlier thought to be 667 or 800 MHz), while MP chips stay at 400 for now. The DP chip is called Fanwood while the MP chip is known as Madison 9M. Uses the E8870 chipset.
An upgraded Deerfield (a low voltage Itanium) will also be launched known as Fanwood LV. The first versions use the 400 MHz bus, while chips using a 667 MHz bus will show up in 2005-Q1.
2005-02-14 Intel Irwindale Prescott based DP processor with 2MB of L2 cache.
2005-03-29 Intel Potomac Prescott based chip for 4- and 8-processor servers. Will have the EM64T bit extensions. Starts at 3.33 GHz and includes 8 MB of L3 cache. Uses the Twin Castle chipset. Part of the Truland platform
2006-07-18 Intel Montecito Dual core IA-64 processor with Switch on Event MultiThreading (SoEMT), (like Niagara) built on a 90 nm process. Expected to improve on Madison 9M's performance by 2.5 times. To include 2 * 1MB of L2 cache, 2 * 12MB of L3 cache and around 1.7 billion transistors.
Consumes "only" 100W. (Foxton was to clock it up to 2.0 GHz when it was running cool enough, but was canceled.)
The 2.0 GHz / 24 MB versions are delayed until Q2 2006.
Will be named 9000 (9015, 9020, 9030, 9040 and 9050). The 9010 is a single core version.