2004-10-18 Intel Dempsey ready for Blackford, Greencreek punch-up

Link to story (The Inquirer)

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2004-11-08 Intel Fanwood / Madison 9M Upgraded Madison with 9 MB of L3 cache. Said to run at 1.6 GHz, and DP chips will include a bus speed increase to 533 MHz (earlier thought to be 667 or 800 MHz), while MP chips stay at 400 for now. The DP chip is called Fanwood while the MP chip is known as Madison 9M. Uses the E8870 chipset.
An upgraded Deerfield (a low voltage Itanium) will also be launched known as Fanwood LV. The first versions use the 400 MHz bus, while chips using a 667 MHz bus will show up in 2005-Q1.

2005-02-14 Intel Irwindale Prescott based DP processor with 2MB of L2 cache.

2005-03-29 Intel E8500 Server chipset made to accompany the 4-processor server (4S) chips Cranford, Potomac and later Paxville and Tulsa. Said to support PCI Express, Serial ATA and DDR-II. Also known as Twin Castle 4S.

2005-03-29 Intel Potomac Prescott based chip for 4- and 8-processor servers. Will have the EM64T bit extensions. Starts at 3.33 GHz and includes 8 MB of L3 cache. Uses the Twin Castle chipset. Part of the Truland platform

2005-10-10 Intel Paxville Dual core server processor. Paxville is the server version of Smithfield. Uses the Twin Castle / Enabled chipsets. Will be known as the Xeon 7000 series MP.

2006-Q1 Intel Greencreek Xeon chipset succeeding Tumwater for dual core processors like Dempsey. Supports the Dual Independent Bus (2S platform).

2006-Q1 Intel Blackford Xeon chipset succeeding Lindenhurst. Supports the Dual Independent Bus (DIB, 2S platform) and Dempsey.

2006-Q2 Intel Dempsey Dual core server processor to succeed Irwindale. An MV Dempsey with a power demand of less than 105 W will also be out. Part of the Bensley platform. Some samples will be out this year. Uses the Greencreek and Blackford chipsets

2006-07-18 Intel Montecito Dual core IA-64 processor with Switch on Event MultiThreading (SoEMT), (like Niagara) built on a 90 nm process. Expected to improve on Madison 9M's performance by 2.5 times. To include 2 * 1MB of L2 cache, 2 * 12MB of L3 cache and around 1.7 billion transistors.
Consumes "only" 100W. (Foxton was to clock it up to 2.0 GHz when it was running cool enough, but was canceled.)
The 2.0 GHz / 24 MB versions are delayed until Q2 2006.
Will be named 9000 (9015, 9020, 9030, 9040 and 9050). The 9010 is a single core version.

2006-Q3 Intel Tulsa Dual-core IA-32 server chip in the Xeon class, succeeding Potomac to launch in 2006. Based on two Netburst cores with Hyperthreading.

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