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2004-12-12 Intel's Whitefield takes four core IA-32 shape

Link to story (The Inquirer)

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2004 Alpha 21464 EV8 Also known as Arana, EV8 or "by far the most aggressive speculative out-of-order execution superscalar RISC processor yet proposed". To include SMT or Simultaneous Multi-Threading. Built on 0.13 um technology at over 1500 MHz. Now canceled while some EV8 technologies will be used in Itanium.

2007-H2 Intel Whitefield Low power, multi-core (4 x Banias with shared cache) server chip, possibly in the Xeon-line, succeeding Potomac, and Tulsa. 4 core version of / follow-on to Woodcrest. Said to be designed in India on a 65nm process, using the original Tanglewood interface. Includes CSI (Common System Interface) with embedded memory controllers to replace the DIB and compete with HyperTransport.
Said to be canceled. CSI will show up first in Tukwila.
Tom's claim that it is still alive.

2008 Intel Tanglewood / Tukwila IA-64 processor originally said to have eight (plus one spare) cores per die and 16-32MB of cache to follow after Montecito. Appears to use parts from a follow-on project to the now canceled Alpha EV8. Said to arrive in 2006 or 2007 and offer "at least seven times the processing" power of Madison. Other rumours claim that HP wants their advanced math libraries on the die in silicon and that it might include a vector engine.
The 8+1 core version (designed in Hudson) is now said to be replaced by a 2-core version designed in Fort Collins.
Recently said to be renamed from Tanglewood to Tukwila due to copyright reasons.
Should use the new CSI bus and socket like Whitefield). Latest info indicates it will include 4 cores with 6x4 MB of L2 cache and an on-bord FB-DIMM memory controller..

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