2004-12-10 AMD Tips Next-Generation Microprocessors Features: AMD Says Multi-Core, DDR3, HyperTransport 3, PCI Express Gen 2 Future

Link to story (Xbit Labs)

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2003-04-22 HyperTransport AMD developed interconnect planned for inter-chip communications in Hammer systems formerly known as Lightning Data Transport (LDT). Supports 1x, 4x and 12x links with bandwidths of 2.5Gb/s, 10 Gb/s and 30 Gb/s in each direction.

HyperTransport II is said to be in the works and will use a new clocking scheme to increase transfer speeds. At least 3 Gb/s (4x at 800 MHz, 3x at 1000 MHz), with an objective of 4 Gb/s (5x/800, 4x/1000) or 5 Gbps (6x/800,5x/1000) (HTT-I clocking is 2x [DDR]).
Thus, HTT-II could provide anywhere from 3.2 to 4.8 Gbits per second for each pair of pins at 800 MHz.
Designed to be backwards compatible with HTT-I.

2004-06-21 PCI Express PC interconnect formerly known as 3GIO. Evolved from PCI and the physical interface of InfiniBand to a serial high bandwidth interface which will be used both as a PCI / AGP replacement and for chip to chip communications. Runs at 2.5 GHz and 0.8 V today, but will move to 5 GHz in PCI Express 2 in 2007-2008, and later to 10 GHz. Provides independent channels for each direction. Multiple bus widths are available:

From PCISIG:
"PCI Express currently runs at 2.5Gtps, or 250MBps per lane in each direction, providing a total bandwidth of 16GBps in a 32-lane configuration. Future frequency increases will scale up total bandwidth to the limits of copper and significantly beyond that via other media without impacting any layers above the Physical Layer in the protocol stack."

Will also spawn a successor to the PCMCIA (PC-Card, CardBus) slot, 3GIO-M, Newcard or ExpressCard, which includes both PCI Express and USB 2.0 interfaces.

2006 DDR-III SDRAM Update of DDR-II planned to run at 800 MHz to 1.2 GHz.

2007 AMD K9 Quad core chips said to succeed the current generation.

2008 AMD K10 Next generation AMD platform with a pin count > 940 pins... Earlier plahnned for 2006...

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