2005-01-19 Intel Alviso Chipset in Napa platform based on Grantsdale, but for notebooks succeeding Montara and Odem from the Centrino line. Likely to be available in several versions with (-GM) and without graphics. Earlier planned for 04-H2. G-version said to include the GMA900 graphics core.
Alviso is part of the Sonoma generation of the Centrino platform.
Napa64 is likely to be a Alviso with support for Merom.
2006-01-05 Intel Yonah Mobile chip, succeeding Dothan in the power optimized notebook segment including HyperThreading and Vanderpool. Will use the Alviso-GM chipset. Includes one (Yonah1 - Core Solo) or two (Yonah2 - Core Duo) Dothan cores with one shared 2MB cache. The cache is dynamically divided between the cores. Runs on a 667 MHz bus, except for the ULV version which uses 533 MHz. Earlier listed as a 90nm chip in 04-H2.
Yonah (sometimes referred to as Jonah) is part of the Napa Centrino platform, succeeding Sonoma.
Named X50: $637, X40: $423, X30: $294, and X20: $241, while X48 and X39 will be low voltage versions.
There will also be a low-end Yonah called 756, below X20, with only one core running at 1.67 GHz and 2MB of cache.
Yonah will be used in future Macs.
Newer info names the chips T2600, T2500, T2400 and T2300 for normal chips, L2400 and L2300 for Low Voltage and U1400 and U1300 for Ultra Low Voltage. Clocked from 1.06 to 2.16 GHz.
2006-07-27 Intel Merom Mobile processor succeeding Prescott-M and Yonah built on a 65 nm process. Accompanied by the Crestine chipset. Recent rumours claim that Merom is a major new core design with multiple cores and, depending on version, 2-4 MB of cache, which will also form the base for the next desktop chip, Conroe. Said to consume about 45W.
Earlier said to launch in 05-H2 or 2007, prototype chips has been out since May of 2006.
Merom is part of the Santa Rosa Centrino platform, succeeding Napa. Said to be used in future Macs.
Bus speed to go up to 800 MHz in 2007-H1.
Will be named T7600, the T7400, the T7200 and T5600.
2008 Intel Common System Interface New bus to compete with HyperTransport for both Pentium and Itanium chips. Processors said to add embedded memory controllers. Delayed from 2007 until perhaps 2009? Said to be included in Tukwila.
2008 Intel Tanglewood / Tukwila IA-64 processor originally said to have eight (plus one spare) cores per die and 16-32MB of cache to follow after Montecito. Appears to use parts from a follow-on project to the now canceled Alpha EV8. Said to arrive in 2006 or 2007 and offer "at least seven times the processing" power of Madison. Other rumours claim that HP wants their advanced math libraries on the die in silicon and that it might include a vector engine.
The 8+1 core version (designed in Hudson) is now said to be replaced by a 2-core version designed in Fort Collins.
Recently said to be renamed from Tanglewood to Tukwila due to copyright reasons.
Should use the new CSI bus and socket like Whitefield). Latest info indicates it will include 4 cores with 6x4 MB of L2 cache and an on-bord FB-DIMM memory controller..
2008 Intel Nehalem Nehalem was a new design built using a 65 nm process with half the die size of a Northwood. Was supposed to use a 1200 MHz (or a 4 GHz bus as some rumours claim) bus and start at 9.60 GHz before continuing to 10 GHz+.
Nehalem is now changed to be the name of the family succeeding Merom, Conroe and Woodcrest, which is 45nm and will include Whitefield, Gainstown and Bloomfield. The Nehalem platform will use the Tylersburg chipset